1. Field of the Invention
This invention relates to a video signal sampling circuit and an image display apparatus including the same.
2. Description of the Prior Art
A video signal sampling circuit for generating a sampling clock signal and sampling a video signal in response to the sampling clock, and outputting the sampled video signal is known. In such a video signal sampling circuit, the frequency and the phase of the sampling clock signal are manually adjusted because vertical and horizontal resolutions of the video signal are respectively different in accordance with the kind of the inputted video signal.
The video signal is supplied from a personal computer and the sampled video signal is supplied to an image display apparatus such as a video projector including a light source and a liquid crystal light valve unit to display an image in accordance with the sampled video signal.
There are variable standards for video signals from personal computers (PC video signal) in which resolutions are different. For example, the VGA signal has resolutions of horizontal 640 pixels.times.vertical 480 pixels, the SVGA signal has resolutions of horizontal 800 pixels.times.vertical 600 pixels, and the XGA signal has resolutions of horizontal 1024 pixels.times.vertical 768 pixels. Moreover, there are the same VGA signal or the same SVGA signal having slightly different horizontal synchronizing frequencies.
FIGS. 4A to 4G show prior art waveforms of PC video signal to be sampled, sampling clock signals, and sampled video signals.
As shown in FIGS. 4A and 4B, the PC video signal SORG is sampled by the sampling clock signal CLS1 of which frequency is lower than the sampling clock signal used for generating the PC video signal. The sampled PC video signal SS1 is distorted as shown in FIG. 4C.
If a frequency of the sampling clock signal is higher than that of the sampling clock signal used for generating the PC video signal as shown in FIG. 4D, the sampled PC video signal SS2 may have a distortion also, as shown in FIG. 4F. Moreover, the waveform of the sampled PC video signal varies with the phase of the sampling clock signal from the horizontal synchronizing.
When a sampling clock signal CLS0 having substantially the same frequency as the sampling clock signal used for generating the PC video signal is used as shown in FIG. 4F, wherein the phase of the PC sampling clock signal CLS0 is suitably adjusted, the sampled PC video signal SS0 in FIG. 4G shows substantially the same waveform as the PC video signal SORG in FIG. 4A.